The production of electronic circuits, for example VLSI circuits, involves a design flow where the electronic function is first written in a logic form on a suitable software platform, then converted to logic gates by synthesiser software. Thereafter, the circuit design flow incorporates a physical design phase using an automatic place and route tool. The resulting circuit design is then analysed for performance.
One of the prime considerations is clock skew effects, caused by slow clock rise times which may cause shoot-through problems if gate switching is too fast. Thus, any circuit which is designed must be tested to ensure that it meets the timing requirements (constraints) at the extremes of operating conditions, that is for both fastest and slowest silicon performance. The paths between state elements of the circuit cannot have too short a delay but also cannot have too long a delay.
Traditionally, the problem of too short a delay, which could result in shoot-through, has been solved after design of the circuit by placing delay elements between the shoot-through sensitive circuit components and then re-placing and re-routing the circuit components in a further physical design step. The insertion of delay elements into the already designed circuit can be difficult if the circuit is congested.
An alternative is to pre-place delay cells as the circuit is designed in the physical design phase. This reduces the component placing problems in a complex circuit and therefore congestion because the delay elements are taken into account at the start of the design procedure. Moreover, problems caused by clock skew are substantially eliminated. However, this approach can be detrimental in terms of worst case timing so it is then important to determine which pre-placed delay elements are indeed necessary to prevent shoot-through. Those delay elements which can be removed from the circuit are so removed, with the result that the remaining components must then be re-positioned to take into account the gap left by the removed delay elements. The re-positioning of the components necessitates re-evaluation of the circuit for shoot-through.
Such re-placing and routing of a complex VLSI design can take many days to complete in computing time and re-analysis of the results.